1 Mbit SPI Serial Flash
A Microchip Technology Company
SST25VF010A
Data Sheet
Block Protection (BP1, BP0)
The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table 5, to be
software protected against any memory Write (Program or Erase) operations. The Write-Status-Regis-
ter (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-
Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are both 0. After
power-up, BP1 and BP0 are set to 1.
Block Protection Lock-Down (BPL)
WP# pin driven low (V IL ), enables the Block-Protection-Lock-Down (BPL) bit. When BPL is set to 1, it
prevents any further alteration of the BPL, BP1, and BP0 bits. When the WP# pin is driven high (V IH ),
the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
Table 5: Software Status Register
Block Protection 1
Status
Register Bit
Protected
Protection Level
0
1 (1/4 Memory Array)
2 (1/2 Memory Array)
3 (Full Memory Array)
BP1
0
0
1
1
BP0
0
1
0
1
Memory Area
None
018000H-01FFFFH
010000H-01FFFFH
000000H-01FFFFH
T5.0 25081
1. Default at power-up for BP1 and BP0 is ‘11’.
Auto Address Increment (AAI)
The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI
programming mode or Byte-Program mode. The default at power up is Byte-Program mode.
?2011 Silicon Storage Technology, Inc.
8
S725081A
10/11
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